Asynchronous Memory Controller with Data Validation A THESIS SUBMITTED FOR THE DEGREE OF MEng ELECTRONICS ENGINEERING

........................................................................................................................... i ACKNOWLEDGEMENTS ................................................................................................... ii CONTENTS ......................................................................................................................... iii CHAPTER 1 – INTRODUCTION ........................................................................................ 1 Report Outline .................................................................................................................... 1 CHAPTER 2 – ASYNCHRONOUS SYSTEMS .................................................................. 3 Clocked v self-timed .......................................................................................................... 3 Acknowledgment generation ............................................................................................. 4 CHAPTER 3 – LITERATURE REVIEW ............................................................................. 6 Delay Line .......................................................................................................................... 6 Completion Detection ........................................................................................................ 7 CHAPTER 4 – TECHNICAL SECTION ............................................................................ 13 Methodology and Design Flow ........................................................................................ 13 Memory Controller Design .............................................................................................. 14 Acknowledgment generation ........................................................................................... 19 CHAPTER 5 – RESULTS ................................................................................................... 23 CHAPTER 6 – DISCUSSION ............................................................................................. 26 Delay line vs data validation ............................................................................................ 26 Future Work ..................................................................................................................... 27 CHAPTER 7 – CRITICAL ANALYSIS ............................................................................. 28 Memory Controller Marios Elia iv | P a g e CHAPTER 8 – CONCLUSIONS ........................................................................................ 30 REFERENCES .................................................................................................................... 31 Memory Controller Marios Elia v | P a g e TABLE OF FIGURES Figure 1 Synchronisation failure [4] ........................................................................................ 4 Figure 2 Acknowledgment generation [4] ............................................................................... 5 Figure 3 Adjustable delay line [7] ........................................................................................... 6 Figure 4 Completion Detection circuit by YUN [8] ............................................................... 7 Figure 5 RESET circuitry [9] .................................................................................................. 8 Figure 6 DONE circuitry [9] ................................................................................................... 8 Figure 7 CMOS implementation of MULLER –C [3] ........................................................... 9 Figure 8 pMOS as a current sensor [5] .................................................................................... 9 Figure 9 graph presented at the transistor's drain [5]............................................................. 10 Figure 10 Amplifier used for amplifying the signal from pMOS [5] .................................... 10 Figure 11 monostable multivibrator [5][10] .......................................................................... 11 Figure 12 Complete system block diagram [5] ..................................................................... 12 Figure 13 Design Flow used [12] .......................................................................................... 14 Figure 14 – Decoder................................................................................................................. 15 Figure 15 Register Bank ........................................................................................................ 16 Figure 16 – SRAM ................................................................................................................... 17 Figure 17 – Multiplexer ........................................................................................................... 18 Figure 18 Delay Line ............................................................................................................. 19 Figure 19 Data Validation ..................................................................................................... 21 Figure 20 Read ACK generation ........................................................................................... 22 Memory Controller Marios Elia vi | P a g e Figure 21 Simulation Results ................................................................................................ 23 Figure 22 Register only testbench ......................................................................................... 24 Figure 23 Module with delay line.......................................................................................... 25 Figure 24 Sampled read/write signal ..................................................................................... 27 Memory Controller Marios Elia 1 | P a g e CHAPTER 1 – INTRODUCTION The constant need for better, faster and more power-efficient electronic systems, has stimulated the need for innovation in every design level. For years, engineers have been pushing the boundaries of Synchronous design, inventing ingenious ways to meet the requirements posed by the electronics industry. Recent years though, have seen an increased focus on Self – Timed system design as an alternative. This paper is a technical report detailing the design of an Asynchronous Memory Controller module. It was specifically created to enable the very-low voltage operation of the Asynchronous version of Intel 8051 microcontroller. While the processor itself can operate across a wide range of supply voltages [1], the Static RAM included within the chip is unable to remain operational when the supply drops below 0.9 V. To overcome this problem, it was proposed to save the most essential data within a Register Bank, in low voltage conditions, thus allowing the system to keep operating; even with decreased functionality. The objective of the memory controller, is to manage all read/write processes for the SRAM and Register Bank, validate the data written in the Register Bank, and produce an acknowledgement signal once the operation is complete. By the end of the project period, a synthesized and functioning module was produced. A number of precautions were taken in order to create a robust design, while simultaneously ensuring that the module is not overengineered or inefficient. Simulations performed on the system’s netlist suggest that the memory controller should operate faultlessly when coupled with the microprocessor. Furthermore, a power-analysis curried out on the final design, indicated that the module consumes very low power due to its simple and effective design.